Bit-Banging

As the title says it all, this is about ‘Banging’ the ‘Bit’. This comes as a handy method for simplifying data transactions over certain interfaces. Here are a few applications where this can be used:

1. Programming a flash/PLD (though complex due to protocols, can be done).
2. Providing clock source to a peripheral where trace connecting clock is unavailable.
3. Data transaction in both Master/Slave mode with certain peripherals. But the complexity increases when in slave mode.

Every Processor provides some pins out for interfacing with peripherals and/or On-Chip components. The pins are multi-functional and they can be used either as a dedicated pins for an On-Chip component or as a General Purpose IO pin ( GPIO). Turning the pin to a GPIO helps us to toggle the state of the pin from HIGH to LOW and vice versa using the code that runs in the Processor.

Consider the below schematic of a Processor-Peripheral interface.

The Peripheral is fed the clock from the Processor. Once the Peripheral is selected through the “Chip Select” signal, the Clock is sent. Then the data to be transmitted is sent through the Pin 2 through this Bit-Banging method. The data is sent as ripples, a sequence of toggles and that is how the name “Bit-Banging” has got its name from. Once the data is processed by the Peripheral, it sends the response back. The response can be read through Pin 3.

The next obvious question would be synchronization to match the speed of the Peripheral and the Processor. How is that done? A little deep into the actual process would reveal us the right calculation of delays and processing sequence that is required.

We see the sequence of steps to be followed in this process. This is required and only this could reveal us the actual timing requirements and the steps to be followed. We’ll consider all scenarios, one by one.

In this case, we have a single Processor that is in “Master Mode”. A component which can initiate communication over an interface is said to be in “Master Mode”. We can have multiple Peripherals connected to the Processor. One such arrangement is shown below.

We can either have a single pin out for Clock, Tx Data and Rx Data or independent pins for each peripheral. In the later case the problem at hand is simple.

In the former, since the pins are said to be “Shared”, the “Chip Selects” are used to differentiate the access. Hence, before each access, the particular component’s Chip Select should be “Asserted” or held low.